Field of the Invention
The present invention relates to a transistor manufacturing method and a transistor.
Background
In the related art, considerations have been made in which a solution process that is inexpensive and suitable for the enlargement of wafer size can be applied to a manufacturing method for transistors. By employing such a solution process, it is possible to manufacture a transistor at a lower temperature than conventional processes. Further, by forming an organic semiconductor layer that uses an organic semiconductor material on a flexible substrate that uses a resin material, it is also possible to manufacture organic transistors having flexibility.
In such a transistor manufacturing method, chemical plating (electroless plating) can be used which is a plating method that utilizes reduction of a material surface according to a contact action. Since electric energy is not used in electroless plating, it is possible to apply plating to a resin material, a glass, and the like as a nonconductor. However, a poor plating material such as a resin material or a glass has weak adhesion to the formed plating film, and the plating easily causes abrasion such as peeling and swelling due to internal stress in the plating film.
Therefore, a method is used in which an etching process is applied to the surface of a substrate by using a chromic acid solution or the like and the surface is chemically roughened. Thereby, the plating film to be formed is formed so as to penetrate into the corrugation of the roughened resin material, and therefore, it is possible to obtain an adhesion force (anchor effect).
In addition, a method (for example, refer to Japanese Unexamined Patent Application, First Publication No. 2008-208389) is disclosed in which a base film that consists of a filler component such as a fine powder silica and a resin composition component is provided on a substrate surface and electroless plating is applied on the base film.